Programmable logic devices (PLDs) are well known. Commonly, a PLD has a plurality of substantially identical logic elements, each of which can be programmed to perform certain desired logic functions. The logic elements have access to a programmable interconnect structure that allows a user to interconnect the various logic elements in almost any desired configuration. The interconnect structure also provides access to a plurality of I/O pins, with the connections of the pins to the interconnect structure also being programmable and being made through suitable I/O buffer or driver circuitry. The PLD may be field programmable or programmable, either wholly or partially, in any other manner. It may be one-time only programmable, or it may be reprogrammable. The term PLD as used herein will be considered broad enough to include all such devices.
As user applications incorporating PLDs evolve to operate at yet higher and higher speeds, and higher frequency signaling standards evolve to support those requirements, it is desirable that the I/O capability of PLDs keep pace with these developments.
In order to achieve successful operation in circuits operating at high speeds, typically greater than 200 Mhz at present, existing I/O signaling standards require a signal waveform having fast edge rate and small output voltage swing, in order to maintain precise phase relationships between the high frequency signals. These two crucial requirements, fast edge rate and small output voltage swing, are physical characteristics inherently in opposition with each other. Overdriving for a faster edge rate directly results in increased output voltage swing. It is therefore becoming increasingly difficult to meet both requirements when the same output current settings are used for both switching and holding states as circuit speeds continue to increase.